The invention relates to methods for the disassembly and assembly of frame structures containing pointers.
The current digital transmission network is plesiochronous, that is, e.g. each 2-Mbit/s basic multiplex system has a dedicated clock independent of any other system. It is therefore impossible to locate a single 2-Mbit/s signal in the bit stream of a higher-order system, but the higher-level signal has to be demultiplexed through each intermediate level down to the 2 Mbit/s level to extract the 2-Mbit/s signal. For this reason, especially the construction of branch connections requiring several multiplexers and demultiplexers has been expensive. Another disadvantage of the plesiochronous transmission network is that equipments from two different manufacturers are not usually compatible.
The above drawbacks, among other things, have led to the introduction of the new synchronous digital hierarchy SDH specified e.g. in the CCITT specifications G.707, G.708 and G.709. The synchronous digital hierarchy is based on STM-N transfer frames (Synchronous Transport Modules) located on several levels of hierarchy N (N=1,4,16. . . ). Existing PCM systems, such as 2-, 8- and 32-Mbit/s systems are multiplexed into a synchronous 155.520-Mbit/s frame of the lowest level of the SDH (N=1). Consistently with the above, this frame is called the STM-1 frame. On the higher levels of hierarchy the bit rates are multiples of the bit rate of the lowest level.
FIG. 1 illustrates the structure of the STM-N frame, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and column. Rows 1-3 and rows 5-9 of the N.times.9 first columns comprise a section overhead SOH, and the row 4 comprises an AU pointer. The rest of the frame structure is formed of a section having the length of N.times.261 columns and containing the payload section of the STM-N frame.
FIG. 2 illustrates a single STM-1 frame which is 270 bytes in length, as described above. The payload section comprises one or more administration units AU. In the specific case shown in the figure, the payload section consists of the administration unit AU-4, into which a virtual container VC-4 is inserted. (Alternatively, the STM-1 transfer frame may contain several lower-level administration units (AU-3) each containing a corresponding lower-level virtual container (VC-3)). The VC-4 in turn consists of a path overhead POH located at the beginning of each row and having the length of one byte (9 bytes altogether), and of the payload section in which there are lower-level frames also comprising bytes allowing interface justification to be performed in connection with mapping when the rate of the information signal to be mapped deviates from its nominal value to some extent. Mapping of the information signal into the STM-1 frame is described, e.g. in the patent applications AU-B-34689/89 and FI-914746.
Each byte in the AU-4 unit has its own location number. The above-mentioned AU pointer contains the location of the first byte of the VC-4 container in the AU-4 unit. The pointers allow positive or negative pointer justifications to be performed at different points in the SDH network. If a virtual container having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock frequency of the virtual container, the data buffer will be filled up. This requires negative justification: one byte is transferred from the received virtual container into the overhead section while the pointer value is decreased by one. If the rate of the received virtual container is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification: a stuff byte is added to the received virtual container and the pointer value is incremented by one.
FIG. 3 shows how the STM-N frame can be formed of existing asynchronous bit streams. These bit streams (1.5, 2, 6, 8, 34, 45 or 140 Mbit/s, shown in the right in the figure) are packed at the first stage into containers C specified by CCITT. At the second stage, overhead bytes containing control data are inserted into the containers, thus obtaining the above-described virtual container VC-11, VC-12, VC-2, VC-3 or VC-4 (the first suffix in the abbreviations represents the level of hierarchy and the second suffix represents the bit rate). This virtual container remains intact while it passes through the synchronous network up to its point of delivery. Depending on the level of hierarchy, the virtual containers are further formed either into tributary units TU or into AU units (AU-3 and AU-4) already mentioned above by providing them with pointers. The AU unit can be mapped directly into the STM-1 frame, whereas the TU units have to be assembled through tributary unit groups TUG and VC-3 and VC-4 units to form AU units which then can be mapped into the STM-1 frame. In FIG. 3, the mapping is indicated by a continuous thin line, the aligning with a broken line, and the multiplexing with a continuous thicker line.
As is to be seen from FIG. 3, the STM-1 frame may be assembled in a number of alternative ways, and the content of the highest-level virtual container VC-4, for instance, may vary, depending on the level from which the assembly has been started and in which way the assembly has been performed. The STM-1 signal may thus contain, e.g., 3 TU-3 units or 21 TU-2 units or 63 TU-12 units. As the higher-level unit contains several lower-level units, e.g. the VC-4 unit contains TU-12 units (there are 63 such units in a single VC-4 unit, cf. FIG. 3), the lower-level units are mapped into the higher-level frame by interleaving so that the first bytes are first taken consecutively from each one of the lower-level units, then the second bytes, etc. Accordingly, when the VC-4 signal contains, e.g., the above-mentioned 63 TU-12 signals, these signals are located in the VC-4 frame as shown in FIG. 2, i.e. the first byte of the first TU-12 signal is located first, then the first byte of the second TU-12 signal, etc. After the first byte of the last signal, i.e. the 63rd TU-12 signal, the second byte of the first TU-12 signal follows, etc. Fours bytes of each TU-12 signal will thus be located on each row of the STM-1 frame, the entire STM-1 frame comprising 4.times.9=36 bytes. In a basic case, one complete TU-12 frame having the length of 500 .mu.s is divided into four consecutive STM-1 frames. The TU-12 frame comprises four pointer bytes V1-V4 so that the first quarter of the TU-12 frame contains the pointer byte V1, the second quarter contains the pointer byte V2, etc. The first two bytes V1 and V2 form the actual TU pointer value; the byte V3 is used for justification; and the byte V4 is reserved for other purposes. The TU-12 pointer, which consists of the bytes V1 and V2, points to the first byte in the VC-12 unit. This first byte is indicated generally by the reference V5. The structure of the TU-12 frame appears more clearly from FIGS. 8 and 13, which will be referred to in more detail below.
The above-described SDH frame structures and the assembly of such structures have been described e.g. in References [1] and [2], which are referred to for more detailed description (the references are listed at the end of the specification).
When, e.g. the above-described TU-1, TU-2 or TU-3 level signals are switched, e.g. in a SDH cross-connect equipment 41 shown in FIG. 4, all signals of the same level of hierarchy to be switched have to be fully synchronous with each other, that is, clocked by the same clock signal edge. In addition, the frames of the signals to be switched have to be equal in phase.
The above-described synchronization may take place in the synchronizing unit 42 of each incoming line, where the payload of the signal coming to the cross-connect equipment 41 is stored in an elastic buffer in synchronization with a clock signal extracted from the incoming signal and is read from the elastic buffer in synchronization with the clock signal of the cross-connect equipment. In order to determine the payload to be written into the elastic buffer and the phase of the payload, the control data contained in the higher-level frames, such as pointers, have to be disassembled. Correspondingly, it is necessary that the higher-level SDH frame structures and associated control data can be added to the payload to be read from the elastic buffer.
The assembly and disassembly of SDH frame structures and pointer information is a complicated operation which has to performed separately for each signal of a certain level of hierarchy. For instance, when the 63 VC-12 signals contained in a single STM-1 frame are synchronized as described above, the AU-4 level pointer contained in the STM-1 frame first has to be processed by an AU-4 processing unit provided for the purpose, but then the frame structure has to be disassembled and the pointer information has to be interpreted independently in each TU-12 channel (63 altogether). Correspondingly, the frame structure and pointer information of each TU-12 channel have to be reassembled independently.
The above-described disassembly and assembly operations have been realized by constructing a single unit for disassembling/assembling the frame structure and control data on a desired level of hierarchy. This unit is then reproduced in a required number. A schematic block diagram illustrating this arrangement is shown in FIG. 5, where the disassembly and assembly of a frame comprising 63 TU-12 channels is used as an example similarly as above. A signal with the STM-1 frame structure is first applied to a common interpretation unit 51, which interprets the AU pointer data and the H4 byte in the path overhead (POH) of the VC-4 container so as to locate the TU-12 frames contained in the frame structure. The interpretation unit 51 then forwards the bytes of each TU-12 channel to a dedicated interpretation unit 52, of which there are thus 63 altogether in this specific case. The interpretation unit interprets the pointer of each TU-12 channel so as to determine the phase of the VC-12 signal. Due to the interleaving of the TU-12 units in the frame structure, each interpretation unit operates for only about 1/63 of the available time. Each VC-12 signal is stored in a dedicated elastic buffer 53. Correspondingly, when the frame structure of the highest level is reassembled, the pointer information of each new TU-12 unit is generated in a dedicated generation unit 54, whereafter the final frame structure is assembled in a common generation unit 55 by combining the payloads from the elastic buffer memories with the new pointers and the new control data. The fill rate of each elastic buffer 53 is monitored by a dedicated monitoring unit 56.
AU and TU pointers as well as their generation and interpretation are described in Reference [1], which is referred to for more detailed description.
In practice, the above-described disassembly and assembly operations may be realized, e.g. by ASIC circuits (Application Specific Integrated Circuit). A problem therewith, however, is the high requirement of hardware, more precisely the large silicon area required, which leads to a high number of components, a large printed circuit board area, and a high number of plug-in units in the equipment. With the 63 TU-12 channels, for instance, this makes it impossible to realize a single disassembly and assembly circuit by a single microcircuit (due to restrictions imposed by present design methods and microcircuit technology). In the prior art arrangement, the memory means for storing the intermediate results of pointer processing (such as D flip-flops, latches, etc.) have the highest requirement of hardware. Modern microcircuit technology does allow the use of RAM memories integrated in a small space, but savings in the silicon area are obtained only in the construction of memory means having a size of 100 bits or more. The utilization of RAM memories does not provide any advantage in the prior art arrangement, as the required memory means are considerably below 100 bits in size.